1. Field of the Invention
The present invention provides a common pass gate layout of a D flip-flop, and more particularly, a common pass gate layout capable of increasing layout density.
2. Description of the Prior Art
In order to design a circuit more efficiently, logic cell libraries composed of commonly used logic circuits are used in the prior art. According to different requirements, a designer must select adaptive logic cell libraries to synthesize logic circuits. In the logic cell libraries, a layout of a master-slave D flip-flop is very important because it occupies a noticeable area in a random logic synthesis block.
Please refer to FIG. 1, which illustrates a schematic diagram of a prior art master-slave D flip-flop 10. The master-slave D flip-flop 10 includes terminals D, CK, Q, and QB for performing a logic operation, which is well known by those skilled in the art, and will not be narrated in detail. As shown in FIG. 1, the master-slave D flip-flop 10 includes four common pass gates 12, 14, 16, and 18, composed by eight MOS (metal oxide semiconductor) transistors, whose gate signals CK1 and CKB are provided by a cell's internal clock buffer 19. Both of the signals CK1 and CKB are transmitted to two p and two n MOS transistors. In a chip implemented by standard logic cell libraries, the master-slave D flip-flop may need a considerable layout area. However, the prior art does not include an efficient method for laying the master-slave D flip-flop, so that chip density is low, and system resources are wasted.